This topic contains general guidelines and techniques for optimizing switch-mode power supply printed circuit board (PCB) layouts specific to PI devices. All example circuits are designed as single-sided PCB layouts to keep the minimal cost. These layout techniques meet the goals of low-cost and ease of manufacture. The two objectives of a good PCB layout are:
Minimize the magnitude and the effect of stray parasitic elements, which exist throughout the circuit traces. These parasitic ”components” are distributed resistances, capacitances, inductances and unwanted magnetic couplings. The placement and arrangement of power supply components, I/O connectors and heat sinks, in short - the entire physical layout of the board directly determines the magnitude and the effects of these parasitic elements. Good layout can improve power supply performance and efficiency as well as reduce unwanted electromagnetic interference (EMI) emissions and the overall product cost.
Maximize conducted heat transfer away from the components that dissipate the most heat. PCB traces, power, or ground planes all can conduct heat away from components and dissipate it into the ambient air. The effectiveness of this method is typically limited to components that dissipate less than 5 Watts (depends on device type and packaging). The conduction of heat though PCB copper is limited by the length, width, and thickness (generally 30 mm or 60 mm / 1 oz or 2 oz) of the circuit traces, as well as the thermal resistance of the PCB material. Positioning hot components near system airflow or keeping thermally sensitive components away from hot components should also be an objective during the PCB layout process.
Safety spacings are also determined during PCB layout. See Application Note AN-15, for more information on safety compliance issues and their impact on PCB layout. Check with your safety representative for more specific information on your end product requirements.
The general layout guidelines provided below should always be used in conjunction with the specific PI component guidelines presented later in the appendix.
The following techniques should be applied to power supplies designed around PI devices. Examples of each technique are presented in the subsequent sections:
Minimize the distance between connected high-current nodes while maximizing the width and thickness of the interconnecting circuit traces. This should minimize the parasitic resistance and inductance of the traces. Keep the path as short and direct as possible. In particular, the parasitic inductance of high-current secondary traces must be minimized. However, avoid connecting switching nodes (for example, trace that connect the transformer to the DRAIN node and the transformer to the secondary diode) with excessively wide traces as this can degrade EMI performance. Keep these traces as short as possible.
Minimize the path length of AC current loops. This should keep the parasitic inductance low while minimizing the magnetic coupling between circuit elements and PCB traces.
Keep the PI device and the switching nodes as far away as possible from the AC input and DC outputs (I/O). This should minimize direct coupling of radiated EMI noise to components and traces near these I/O ports, which helps reduce conducted EMI.
Use identical parallel-connected output capacitors as needed. This keeps the impedance of the secondary AC current paths equal, which tends to make the capacitors share the ripple current more evenly increasing overall reliability. Therefore, the PCB trace-length from output diode to the caps and, then, from the caps back to the transformer must be equal in length, for all paralleled output capacitors. Otherwise, the capacitor with the shortest trace length will conduct the highest portion of the ripple current and dissipate more power than the others, which may potentially decrease its life span.
Place the bulk capacitor in a manner so as to minimize the area of the loop formed by the bulk capacitor, transformer, and PI device.
Maintain adequate spacing between high-voltage primary nodes and all other lower voltage nodes. This helps prevent arcing, which can damage power supply components and cause them to fail.
Use through-hole components to bridge adjoining traces over ground plane copper or power train traces. This will minimize the need for jumpers and reduce PCB layout complexity.
Keep heat sensitive parts away from parts that dissipate a lot of heat. For example, hot heat sinks should not touch electrolytic capacitors or other heat sensitive parts physically . If the design is convectively cooled, pay attention to the likely airflow patterns. Do not put temperature sensitive components in the heat shadow of a hot part. Additionally, do not put parts that need air areas that will get little airflow.
Use a single point (Kelvin) connection at the negative terminal of the input filter capacitor for the source pin or pins. This should help prevent DRAIN currents from interfering with device operation.
Minimize the path length of all components connected to a PI device pin. Those pins that have relatively high input impedances, such as the CONTROL (C), MULTI-FUNCTION (M), EXTERNAL CURRENT LIMIT (X) and VOLTAGE MONITOR (V) pins tend to be sensitive to noise. Minimize the distance from these pins to all external components connected to them. Pay special attention to the V pin as it has a very high impedance. See the TOPSwitch-HX datasheet layout considerations for details.
Common-mode input surge currents should be diverted away from the PI device SOURCE pins. The bias supply’s return path should be connected to the primary (bulk) input capacitor, a safe distance from the device SOURCE pins.
Y-type EMI capacitors should be connected between the primary positive (+bulk) DC bus input and the secondary return. Both connections should be made as close to the transformer pins as possible. If the Y capacitor needs to be connected to the primary return (bulk), provide a separate trace that terminates directly to the bulk capacitor (Kelvin connection).
The tab (heat sink) on PI devices in the Y-package must not be electrically connected to the primary return node. The component tab is internally connected to SOURCE pin and must be left disconnected from the rest of the power supply circuitry. Any electrical contact between the heat sink and the SOURCE pin may allow currents to circulate between the SOURCE and the heat sink.
Connect all P and G package SOURCE pins to the PCB primary return plane, to maximize heat transfer to the board.
Refer to the datasheet of each device for layout examples.